Altering the FPGA clock frequency of the Mojo

The Spartan 6 FPGA that comes with the Mojo uses a default clock frequency of 50 MHz.  While this is sufficient for almost all tasks, there are times when it might be necessary to increase that.  For example, I have a particular use-case that requires a 14-bit PWM signal to be output with a frequency of at least 15 kHz, which implies that the base clock frequency should be at least 250 MHz.

Luckily enough, the Spartan 6 on the Mojo, which has a speed grade of -2, is capable of clock speeds up to 375 MHz, and so is suitable for my purposes.  In addition, the Xilinx Core Generator tool that comes with ISE makes it very easy to change the on-board clock divisor in order to provide a faster clock.

Xilinx Core Generator

Xilinx Core Generator is a tool that allows modules implementing pre-compiled functionality into your FPGA project.  These modules are typically the Intellectual Property of Xilinx, and so you don’t get direct access to the source code (unfortunately), however they allow access to fully tested chunks of code that can significantly speed up the development of your project.

On ISE, open Tools –> Core Generator.

The first thing you will have to do is to start a new project (in the file menu), and tell the project about the hardware we’re using, and how we would like the cores to be generated.

For the Mojo, set the “Part” options as follows:

  • Family: Spartan6
  • Device: xc6slx9
  • Package: tqg144
  • Speed Grade: -2

In “Generation”:

  • Change “VHDL” to “Verilog”
  • Change Vendor to “ISE”
  • For “Preferred Simulation Model”, select “Structural”

Clocking Wizard

Rather than altering the frequency of the clock itself — which would require a physical alteration of the Mojo’s hardware — we will use the Core Generator to create a module that takes the 50 MHz clock as an input, and outputs a new clock at the desired frequency.  This is illustrated in the schematic at the top of this page, where the coregen_clk module at the top-left of the diagram takes clk as input, and outputs a new clock that is then passed to the remainder of the FPGA components.

In the left-hand window of the Core Generator Application, open “FPGA Features and Design”, “Clocking”, and click on the “Clocking Wizard”.  The main window should now display a brief description of this component, as well as a series of actions that appear as web-links.  If all is well, one of the available actions should be “Customize and Generate”.  Click on this now.

Screen Shot 2016-01-13 at 2.36.18 PMAfter a few seconds, a new application window should open.  On the left hand-side is a schematic representation of the desired device, as shown here.

This shows a simple module with only two inputs and two outputs:

  • Inputs:
    • CLK_IN1 — the base 50 MHz clock of the Mojo
    • RESET — the clock will stop pulsing while this is pulled high
  • Outputs:
    • CLK_OUT1 — the high frequency clock output to be provided to the remainder of the FPGA
    • LOCKED — a logical signal to indicate that the input and output clocks are properly phase-locked

Despite the simplicity of this, we will make it even simpler.  Since we have no need to suppress clock ticks, and since we will just trust that the phase-locking is satisfactory, we can eliminate the RESET and LOCKED signals.

To implement our new clock, you should change the component name to something sensible (“coregen_clk” perhaps), and set the frequency of the input clock to 50 MHz.

Click “next”.

Set the output frequency of CLK_OUT1 to 300 MHz.

Click “next”.

Remove the check marks from RESET and LOCKED.  You should see that the module schematic changes appropriately.

Click “next”.

No changes here.

Click “next”.

Change the port names if you like.

Click “next”.

Now the configuration is complete, click “Generate”.

This will begin the process of creating the new module, and once this is done, it can be imported into your ISE Verilog project using “Project” –> “Add Source”.  It is found in the ipcore_dir of your project, and you need to be sure to add coregen_clk.v and coregen_clk.xco.

In the Verilog source for your project, add the following lines to the top file.

wire fastclk;
coregen_clk coregen_clk(

This inputs clk to the new module and supplies the output to the fastclk wire.  It is this wire that should be provided as a clk signal to the remainder of the project, and not clk.  That way, the entire project will make use of the 300 MHz clock.


IMG_2911This image shows a scope trace of a 14-bit PWM output (in yellow) running off a 300 MHz clock.  You can see that the period of the PWM signal is ~52 us, which is consistent with a clock frequency of 300 MHz.

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