In a previous post I outlined a preliminary plan for how to configure an FPGA to characterise the response of a photoresistor to illumination by an LED whose brightness was controlled via the duty cycle of a PWM signal. In that post I wrote that the required behaviour suggested a state machine with only two states: idle and scanning. Subsequent experiments with the FPGA have convinced me that that is not the correct approach, and I have now settled on a state machine using four different states: idle, set, read, write. The flow between states is shown in the following diagram.
You can see that this results in very simple states, that are relatively easy to implement and test.
Each state starts by setting all the module’s parameters to the desired values. Care is taken to ensure that every single parameter is set in each state so that no assumptions are made on the behaviour of the preceeding state and, more importantly, so that the FPGA synthesiser does not deduce that any latches are required. The state then performs one or more tests to determine if the system should remain in that state or if it needs to transition.
This state-machine has been implemented in Verilog, and test-bench simulations (after considerable debugging) show that the expected sequence of digital values is produced. It hasn’t yet been possible to simulate the full module since it relies on input from an external ADC. It is, of course, possible to do the simulation, however finding the right sequence of digital inputs to the Serial Peripheral Interface (SPI) bus is proving difficult, and it seems that it might just be faster to test the physical implementation on the actual FPGA.